The present invention is generally related to an integrated circuit having provisions for aligning ports developed using different layout methodologies and, more particularly, to an integrated system and method for aligning ports and providing for signal buffering within a common area of integrated circuit real estate.
It is common in integrated circuit design for various methodologies to be utilized in laying out the signal wiring, or routing, which forms signal paths for signals to travel. Unfortunately, because of the inherent differences in these methodologies, it is common for there to be resulting mismatches in port alignments. As a result, the ports on various blocks of circuitry on an integrated circuit may not precisely line up for easy and direct interconnection. Thus, efforts must be taken to provide for an interface to link the different pieces of circuitry, This typically entails additional wiring to link the mis-aligned ports.
In order to combat the degradation in signal quality due to long signal paths, it is common to buffer the signals in order to retain proper signal timing and amplitude. Buffering of signals has typically been carried out separately from providing for linking of mis-aligned ports. This has resulted in integrated circuit real estate being utilized separately for aligning mis-aligned ports and for providing for appropriate buffering. As integrated circuit real estate is typically at a premium, addressing these two issues separately has meant greater usage of integrated circuit real estate.
FIG. 1 illustrates an example of two sets of ports from separate blocks of circuitry on an integrated circuit 200. Here it can be seen that a first set of ports 10, 11, 12 and 13 are located in a one area 1 on the integrated circuit 200. A second set of ports 14, 15, 16 and 17 are provided in a separate area 2 of integrated circuit 200. It will be noted that ports 10 and 14 represent a signal path A; that ports 11 and 15 represent a signal path B; that ports 12 and 16 represent a signal path C and that ports 13 and 17 represent a signal path D. Axes 100, 101, 102 and 103 help to show that the above pairs of ports do not directly align with one another.
With reference to FIG. 2 one typical technique of aligning ports is shown. Here a linking area 25 is utilized wherein bridge traces 20, 21, 22 and 23 art used to connect a first set of ports (ports 10, 11, 12 and 13, respectively) with a second set of ports (ports 14, 15, 16 and 17 respectively), via wiring traces (30, 31, 32 and 33 respectively) and signal buffering blocks (40, 4142 and 43 respectively) in common area 35. The use of linking area 25 to provide for bridging traces 20, 21, 22 and 23 separate from common area 35 requires consumption of integrated circuit real estate which could otherwise be devoted to other purposes. This is expensive and wasteful, particularly with complex integrated circuits in which thousands upon thousands of semiconductor gates are implemented on the integrated circuit.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
The present invention provides an integrated system and method for aligning mis-aligned ports within an integrated circuit designed using various layout methodologies.
Briefly described, in architecture, the system can be implemented as follows. There is provided an output port for transmitting a signal to a second port. The second port is designed to receive the signal. There is provided an alignment link for electrically connecting the first port with the second port. The alignment link is made up of a signal buffer for buffering a signal traveling along the alignment link between the first port and the second port.
The present invention can also be viewed as providing a method for aligning ports in an integrated circuit In this regard, the method can be broadly summarized by the following steps: extending a first port from one area into a common area; extending a second port from another area into the common area; linking the first port to the second port within the common area via an alignment link composed of a wiring trace and a signal buffer.